dc.contributor.author | Nagareddy, VK | |
dc.contributor.author | Barnes, MD | |
dc.contributor.author | Zipoli, F | |
dc.contributor.author | Lai, KT | |
dc.contributor.author | Alexeev, AM | |
dc.contributor.author | Craciun, MF | |
dc.contributor.author | Wright, CD | |
dc.date.accessioned | 2017-04-03T09:30:32Z | |
dc.date.issued | 2017-02-27 | |
dc.description.abstract | Graphene oxide (GO) resistive memories offer the promise of low-cost environmentally sustainable fabrication, high mechanical flexibility and high optical transparency, making them ideally suited to future flexible and transparent electronics applications. However, the dimensional and temporal scalability of GO memories, i.e., how small they can be made and how fast they can be switched, is an area that has received scant attention. Moreover, a plethora of GO resistive switching characteristics and mechanisms has been reported in the literature, sometimes leading to a confusing and conflicting picture. Consequently, the potential for graphene oxide to deliver high-performance memories operating on nanometer length and nanosecond time scales is currently unknown. Here we address such shortcomings, presenting not only the smallest (50 nm), fastest (sub-5 ns), thinnest (8 nm) GO-based memory devices produced to date, but also demonstrate that our approach provides easily accessible multilevel (4-level, 2-bit per cell) storage capabilities along with excellent endurance and retention performance-all on both rigid and flexible substrates. Via comprehensive experimental characterizations backed-up by detailed atomistic simulations, we also show that the resistive switching mechanism in our Pt/GO/Ti/Pt devices is driven by redox reactions in the interfacial region between the top (Ti) electrode and the GO layer. | en_GB |
dc.description.sponsorship | This work was carried out under the auspices of the EU FP7
project CareRAMM. This project received funding from the
European Union Seventh Framework Programme (FP7/2007-
2013) under grant agreement no. 309980. The authors are
grateful for helpful discussions with all CareRAMM partners,
particularly Prof. Andrea Ferrari and Ms. Anna Ott at the
University of Cambridge, and Drs. Abu Sebastian and Wabe
Koelmans at IBM Research Zurich. We also gratefully
acknowledge the assistance of the National EPSRC XPS
User’s Service (NEXUS) at Newcastle University, U.K. (an
EPSRC Mid-Range Facility) in carrying out the XPS measurements | en_GB |
dc.identifier.citation | ACS Nano, 2017, 11 (3), pp 3010–3021 | en_GB |
dc.identifier.doi | 10.1021/acsnano.6b08668 | |
dc.identifier.uri | http://hdl.handle.net/10871/26924 | |
dc.language.iso | en | en_GB |
dc.publisher | American Chemical Society | en_GB |
dc.relation.url | https://www.ncbi.nlm.nih.gov/pubmed/28221755 | en_GB |
dc.subject | flexible memory | en_GB |
dc.subject | graphene oxide | en_GB |
dc.subject | multilevel memory | en_GB |
dc.subject | nonvolatile memory | en_GB |
dc.subject | resistive switching | en_GB |
dc.subject | titanium oxide | en_GB |
dc.title | Multilevel ultrafast flexible nanoscale nonvolatile hybrid graphene oxide-titanium oxide memories | en_GB |
dc.type | Article | en_GB |
dc.date.available | 2017-04-03T09:30:32Z | |
dc.identifier.issn | 1936-0851 | |
exeter.place-of-publication | United States | en_GB |
dc.description | This is the author accepted manuscript. The final version is available from the publisher via the DOI in this record. | en_GB |
dc.identifier.journal | ACS Nano | en_GB |
dc.identifier.pmid | 28221755 | |