Nanoscale Carbon-Based Memory Devices

Abstract

Amorphous carbon-based memories have gained traction in recent years due to their good scalability and switching performance and are an important contender to close the performance gap between fast but volatile DRAM and slow but non-volatile flash memory. A writing and erasing process driven by the electrically induced formation and rupture of a conductive filament permits switching times in the range of a few nanoseconds. Further, the memristive property of amorphous carbon allows the implementation of beyond von Neumann computation paradigms. However, ‘pure’ amorphous memories have a low cyclic endurance. To overcome this and to exploit beyond von Neumann computation, devices based on oxygenated amorphous carbon were employed here.

The first part of this thesis evaluated the switching performance and data retention capabilities of tetrahedral amorphous carbon memories. Switching times below 10 ns were achieved for the SET as well as for the RESET times. An energy consumption below 1 pJ was obtained, while data could be retained for more than 300 s at 450 °C. Further, evidence was provided that the SET process is not induced by an electric field alone.

A finite-element simulation was employed in the second part of this thesis to reproduce the experimentally determined conductivity of tetrahedral amorphous carbon (ta-C) memory devices and to shine light on the conditions at the onset switching from the high to low resistance states (dielectric breakdown). The maximum temperature observed at dielectric breakdown was 1615 K. It was found that a reduction of the lateral cell radius from 25 nm to 15 nm and 10 nm increases the switching performance by reducing the switching current from 34 µA to 20 µA and 8 µA.

The third part of this thesis evaluated the switching performance, temperature stability, multilevel storage and memcomputing capabilities of oxygenated amorphous carbon. Switching times below 10 ns for both, SET and RESET were demonstrated. A 3-level (1 1 /2 bits) data storage was achieved using three different resistance states. Further, a memcomputing approach was implemented using a base-16 accumulation response with energy consumptions as low as <100 fJ per pulse. Additionally, a finite element simulation of a device in the low resistance state (LRS) was used to illustrate the correlation between device resistance and Joule heating effects.